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N584HP300 d ata s heet release date: jul . 20 1 6 - 1 - version a 2 .0 n5 84hp300 data sheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for r efer ence purposes of powerspeech ? based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvoton.com
N584HP300 d ata s heet release date: jul . 20 1 6 - 2 - version a 2 .0 table of contents 1. g eneral d escription ................................ ................................ ................................ ............. 3 2. f eatures ................................ ................................ ................................ ............................... 3 3. p ad d escription ................................ ................................ ................................ ................. 5 4. b lock d iagra m ................................ ................................ ................................ ..................... 6 5. e lectrical c haracteristics ................................ ................................ ................................ ..... 7 5.1 absolute maximum ratings ................................ ................................ ................................ .................... 7 5.2 dc parameters ................................ ................................ ................................ ................................ ........ 7 5.3 ac parameters ................................ ................................ ................................ ................................ ........ 8 6. t ypical a pplication c ircuit ................................ ................................ ................................ . 9 7. r evision h istory ................................ ................................ ................................ ................ 11
N584HP300 d ata s heet release date: jul . 20 1 6 - 3 - version a 2 .0 1. g eneral d escription n584h p300 (otp) is a 4 - bit microcontroller - based s peech synthesizer with pwm mode output to drive the speaker directly. the synthesizer contains one voice - channel and/or dual tone melody . it has ultra i / o tm to simplify the procedure of defining the output pattern, besides, it also includes 4 - level low vol tage detection function . the n584 hp300 built - in otp to cover following rom version bodies: n584h h009 h010 h019 h0 20 h029 h030 h039 h040 rom (kbit) 300 300 620 620 940 940 1260 1260 *duration 12 12 24 24 37 37 49 49 i/o pins 4 8 4 8 4 8 4 8 n584h h060 h0 7 0 h120 h170 h210 h260 h300 rom (kbit) 1740 190 0 3340 4460 5740 7020 7980 *duration 68 73 131 175 225 275 312 i/o pins 8 8 16 16 16 16 16 note 1 : the duration time is based on 4 - bit nm4 at 6 khz sampling rate 2. f eatures ? o perating v ol tage and cpu frequency : ? 1 . 8 ~ 5.5 v (fcpu = 4 mhz ) ? 2.0 ~ 5.5 v (fcpu = 8 mhz) ? s peech synthesis ? 1 - channel voice ? dual t one melod y w/ 8 octaves ? 4 - bit nm4 ? build in internal oscillator (trim) ? build in pwm direct drive circuit ? programmable sample rate ? provide s p ower management to save current consumption ? 4 / 8 mhz system clock, with ring type oscillator ? s top mode for stopping entire devices operation ? provides 16 i/o ? high sink current capability
N584HP300 d ata s heet release date: jul . 20 1 6 - 4 - version a 2 .0 ? support capture timer to implement up to 8 capture sensor key ? p rovid e s 224*4 bits ram ? provides 6 4 k*10 of program data ? provides ir carrier generato r (38 khz or 56 khz) ? provides w atch d og t imer (wdt) ? provides low v oltage r eset (lvr: 1.7v, 1.9v) ? prov ides low voltage detection (lvd: 2.2v, 2.4v, 3.0v, 3.3v) ? share d rom for voic e and program storage ? support s powerscript tm for developing codes eas il y ? full - fledged development system ? source - level ice debugger ( powerscript tm format) ? event synchronization mechanism ? u ser - friendly gui environment ? it has ultra i/o tm to simplify the defin ed output pattern
N584HP300 d ata s heet release date: jul . 20 1 6 - 5 - version a 2 .0 3. p ad d escription note: as program otp, the bp 0 1 ~ bp03, vdd, vss, v33o, /reset and vpp pin will be used. p ad name i / o f unction bp00 ~ bp03 i/o bi - directional i/o port 0 , defined as input or output . a s input , it can be set as pull - high , pull - low or floating . a s output , it is defined as cmos . bp03 can also be defined as ir carrier output . bp10 ~ bp13 i/o bi - directional i/o port1 , defined as input or output . a s input , it can be set as pull - high , pull - low or floating . a s output , it is defined as cmos . bp 2 0 ~ bp 2 3 i/o bi - directional i/o port 2 , defined as input or output . a s input , it can be set as pull - high , pull - low or floating . a s output , it is defined as cmos . bp 3 0 ~ bp 3 3 i/o bi - directional i/o port 3 , defined as inp ut or output . a s input , it can be set as pull - high , pull - low or floating . as output , it is defined as cmos . vdd , vdd_io - power supply vss , vss_io - ground v33o - 3.3v regulator output vpp - positive high voltage 7.5v input during otp memory writer mod e. nc for normal operation mode pwm + o pwm drive positive output pwm - o pwm drive negative output vdd _spk - power supply for pwm drive vss _spk - ground for pwm drive test - test p in /r e s e t i chip reset input with schmitt trigger, internal pull - high
N584HP300 d ata s heet release date: jul . 20 1 6 - 6 - version a 2 .0 4. b lock d iagra m
N584HP300 d ata s heet release date: jul . 20 1 6 - 7 - version a 2 .0 5. e lectrical c haracteristics 5.1 a bsolute m aximum r atings i tem s ymbol c onditions r ated v alue u nit power supply vdd C vss - - 0.3 ~ +7.0 v input voltage v in all inputs vss - 0.3 ~ vdd+0.3 v storage temp. t stg - - 55 ~ +150 ? c operating temp. t opr - 0 ~ +70 ? c note: operating the device under conditions beyond those indicated above may cause permanent damage or affe ct device reliability. 5.2 dc p arameters (vdd ? vss = 4.5v, vdd _spk - vss _spk =4.5v, ta = 25 ? c; no lo a d, unless otherwise specified) p arameter s ym c onditions m in t yp m ax u nit operating voltage v dd fcpu = 4 mhz fcpu = 8 mhz 1.8 2. 0 5.5 5 . 5 v operating current i op fcpu =8 mhz, vdd=4.5v 5.0 ma fcpu =8 mhz, vdd=3.0v 3.0 standby current i sb vdd=4.5v 3 1 0 ? oh vdd=3.0v,vout=2.6v - 5 - 6 ma vdd=4.5v,vout=2.6v - 30 output low current (bp0, bp1,bp 2,bp3) i ol vdd=3.0v,vout=0.4v 8 12 ma vdd=4.5v,vout=1.0v 34 pwm driver current ipw rl=8 ? pl vdd=4.5 v 150k 1m ? lvd lvd_sel[1:0] = 11 3.14 3.3 3.47 v lvd_s el[1:0] = 10 2.85 3.0 3.15 v lvd_sel[1:0] = 01 2.28 2.4 2.52 v lvd_sel[1:0] = 00 2.09 2.2 2.31 v
N584HP300 d ata s heet release date: jul . 20 1 6 - 8 - version a 2 .0 5.3 ac p arameters ( vdd ? vss = 4.5v, ta = 25 ? c; unless otherwise specified) p arameter s ym c onditions m in t y p m ax u nit main - clock f requency fosc 8 mhz 7. 9 5 8 . 19 8.4 4 mhz frequency d eviation fosc=8 mhz , vdd=2.2 ~ 5.5v 3 5 % ? f f (min) (min) (max) fosc fosc fosc ?
N584HP300 d ata s heet release date: jul . 20 1 6 - 9 - version a 2 .0 6. t ypical a pplication c ircuit 3 - battery application notes: 1. in pcb layout, vss_spk should be connected t o vss; and vdd_spk should be connected to vdd 2. the c1 capacitor 0.1uf is recommended to prevent the ic from hang - up as battery power bouncing. for power line layout in extended length , suggest c1 to be 1uf 3. the c2 capacitor 4.7uf shunts between vdd an d gnd is to stabilize power noise 4. the c3 capacitor 0.1uf shunts bet ween /reset and gnd is for power reset stability 5. the v33o capacitor value is 0.1uf. it is for regulator power stability on 3 - battery applications 6. bpxy means i/o pins. x: 0 ~ 3; y: 0 ~ 3
N584HP300 d ata s heet release date: jul . 20 1 6 - 10 - version a 2 .0 2 - battery application notes: 1. in pcb layout, vss_spk should be connected to vss; and vdd_spk should be connected to vdd 2. the c1 capacitor 0.1uf is recommended to prevent the ic from hang - up as battery power bouncing. as power line is long, suggest c1 to be 1uf 3. the c2 capacitor 4.7 uf shunts between vdd and gnd is to stabilize power noise 4. the c3 capacitor 0.1uf shunts bet ween /reset and gnd is for power reset stability 5. bpxy means i/o pins. x: 0 ~ 3; y: 0 ~ 3
N584HP300 d ata s heet release date: jul . 20 1 6 - 11 - version a 2 .0 7. r evision h istory version date substantial change s page a 1 . 0 sep . 20 15 initial release a2.0 jul. 2016 revise application circuits 8, 9 important notice nuvoton products are neither intended nor warranted for usage in s ystems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, insecure usage. insecure usage includes, but is not limited to: equipment for surgical implemen tation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuv oton.

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